ASIC Verification Engineer (Verilog)

Кадровое агентство

JCat

Статус

Вакансия находится в архиве

Условия работы

Город

Санкт-Петербург, м. Московские ворота   –   на карте

Заработная плата

По договоренности

График работы

Полный рабочий день

Условия

- Official registration in accordance with the Labor Code of the Russian Federation;

- Opportunity to work in the leading company of the industry;

- Work in an international company;

- Assistance with employee relocation;

- Opportunity to use English every day at work.

Обязанности

- Develop functional models for analog and mixed-signal circuits using Verilog or similar languages

- Write verification specifications based on requited test cases

- Top level digital verifications

- Develop test benches in Verilog or similar languages/environments to verify the top level functions of full chips

- Run verification test benches and communicate results to the team for any fixes/improvements [#3454762#]

Требования к кандидату *

Образование

Среднее

Опыт работы

От 2 лет

Требования

- BA/BS Degree or higher in electrical engineering

- Experience with analog and digital circuit design

- Understanding of Analog schematic and experience with Cadence Virtuoso

- Experience with digital design languages, such as Verilog/SystemVerilog