• Разработка топологии СБИС СнК (система на кристалле) в САПР Cadence. • Проведение статического временного анализа быстродействия. • Проведение статического и динамического анализа мощности, IRdrop. • Проведение формальной верификации проекта. • Проведение физической верификации проекта. Backend Design Engineer (VLSI SoC layout designer) Requirements • VLSI SoC (system-on-chip) backend design experience with using Cadence CAD. • Knowledge of Low Power flow. • EDI, ETS, EPS and Conformal design environment work experience. • 130 nm and less design rule work experience. • Knowledge of programming languages (Tcl, Perl, etc.) is a plus. • Higher education. • English knowledge. • Work experience in the field is not less than 3 years. Duties • VLSI SoC backend design in Cadence CAD. • Static timing analysis (STA). • Static and dynamic power analysis, IRdrop. • Formal verification. • Physical verification. |