Senior ASIC Digital Design Engineer (Verilog)

Кадровое агентство

JCat

Статус

Вакансия находится в архиве

Условия работы

Город

Санкт-Петербург, м. Московские ворота   –   на карте

Заработная плата

По договоренности

График работы

Полный рабочий день

Условия

- Official registration in accordance with the Labor Code of the Russian Federation;

- Opportunity to work in the leading company of the industry;

- Work in an international company;

- Assistance with employee relocation;

- Opportunity to use English every day at work.

Обязанности

- Development and verification of digital block architectures and RTL design for various functions including control state machine, IO controllers, digital signal processing (DSP), and multiple clock domain interface management;

- Work with other digital or mixed-signal designers to define specifications for digital blocks and interfaces;

- Analyze architecture, RTL design for optimal performance, area and power constraints trade-offs;

- Document detailed block and top-level specifications;

- Perform block level RTL design and verification using industry leading EDA tools

- Lead comprehensive design reviews;

- Support backend design flow, including RTL synthesis, clock tree synthesis, scan and DFT insertion, place and route, and netlist verification;

- Collaborate with analog design engineers, CAD, systems engineering, test engineering and applications teams to ensure define optimal DFT, DFM features and achieve rapid silicon bring-up and time to production release;

- Participate in the bring-up of silicon prototypes;

- Analyze circuit for failure root cause analysis, investigate anomalous observations in silicon across various conditions, including PVT variations, and propose solutions. [#3454785#]

Требования к кандидату *

Образование

Высшее

Опыт работы

От 3 лет

Требования

- . or Ph.D. with 5 years of experience in Electrical Engineering

- Proficiency with EDA tools and design languages including Verilog/SystemVerilog

- Extensive experience in digital block verification strategies

- Understanding of digital design flow from architecture design to sign-off

- Experience with DSP concepts, circuits, architectures, and implementation

- Ability to communicate and work effectively with geographically distributed teams of mixed-signal, digital, layout, and verifications engineers

- Ability to work independently and drive solutions to challenging problems

- Good understanding of modeling signal processing algorithm using Matlab or Simulink

- Experience in performing synthesis, static timing analysis, and netlist verifications

- Understanding of digital backend flow for Place & Route (PNR)

- Experience in digital DFT flow (stuck-at / TDF scan insertion and ATPG)

- Experience in complex finite state machine design