Digital Design and Verification Engineer (Verilog)

Кадровое агентство

JCat

Статус

Вакансия находится в архиве

Условия работы

Город

Гурьевск   –   на карте

Заработная плата

По договоренности

График работы

Полный рабочий день

Условия

Official registration in accordance with the Labor Code of the Russian Federation;

- Opportunity to work in the leading company of the industry;

- Work in an international company;

- Assistance with employee relocation;

- Opportunity to use English every day at work.

Обязанности

- Development and verification of digital block architectures and RTL design for various functions including control state machine, IO controllers, digital signal processing (DSP), and multiple clock domain interface management;

- Analyze architecture, RTL design for optimal performance, area and power constraints trade-offs;

- Document detailed block and top-level specifications;

- Perform block level RTL design and verification using industry leading EDA tools;

- Support backend design flow, including RTL synthesis, clock tree synthesis, scan and DFT insertion, place and route, and netlist verification;

- Collaborate with analog design engineers, CAD, systems engineering, test engineering and applications teams to ensure define optimal DFT, DFM features and achieve rapid silicon bring-up and time to production release;

- Develop functional models for analog and mixed-signal circuits using Verilog or similar languages;

- Write verification specifications based on requited test cases;

- Top level digital verifications;

- Develop test benches in Verilog or similar languages/environments to verify the top level functions of full chips;

- Run verification test benches and communicate results to the team for any fixes/improvements. [#3449405#]

Требования к кандидату *

Образование

Среднее

Опыт работы

От 2 лет

Требования

- BA/BS Degree or higher in electrical engineering;

- Understanding of analog circuits;

- Experience with digital design languages, such as Verilog/SystemVerilog;

- Experience with DSP concepts, circuits, architectures, and implementation;

- Good understanding of modeling signal processing algorithm using Matlab or Simulink.

Desired characteristics:

Knowledge scripting languages such as Perl / Python

Ability to communicate and work effectively with geographically ditributed teams of mixed-signal, digital, layout, and verifications engineers

Understanding of digital design flow from architecture design to sign-off